Anusha
01-17-2007, 08:04 PM
Read the full story here (http://www.dailytech.com/article.aspx?newsid=5743).
HP Lab Researchers have created a new “field programmable nanowire interconnect" (FPNI) architecture, a variation on the FPGA technology, that could allow chip makers to place eight times the number of transistors currently possible on standard 45nm field programmable gate array, or FPGA, chips.
Stan Williams, an HP Senior Fellow and director, said in a press statement “As conventional chip electronics continue to shrink, Moore’s Law is on a collision course with the laws of physics. Excessive heating and defective device operation arise at the nanoscale. What we’ve been able to do is combine conventional CMOS technology with nanoscale switching devices in a hybrid circuit to increase effective transistor density, reduce power dissipation, and dramatically improve tolerance to defective devices.”
Current conventional FPGA chips use 80 to 90 percent of their CMOS for signal routing, leaving a relatively small portion for logic processing transistors. With the new FPNI approach, all logic operations will be performed in the CMOS (complementary metal oxide silicon) while most of the signal routing will take place in a nanoscale crossbar switch structure which will be placed on top of the CMOS.
HP Lab Researchers have created a new “field programmable nanowire interconnect" (FPNI) architecture, a variation on the FPGA technology, that could allow chip makers to place eight times the number of transistors currently possible on standard 45nm field programmable gate array, or FPGA, chips.
Stan Williams, an HP Senior Fellow and director, said in a press statement “As conventional chip electronics continue to shrink, Moore’s Law is on a collision course with the laws of physics. Excessive heating and defective device operation arise at the nanoscale. What we’ve been able to do is combine conventional CMOS technology with nanoscale switching devices in a hybrid circuit to increase effective transistor density, reduce power dissipation, and dramatically improve tolerance to defective devices.”
Current conventional FPGA chips use 80 to 90 percent of their CMOS for signal routing, leaving a relatively small portion for logic processing transistors. With the new FPNI approach, all logic operations will be performed in the CMOS (complementary metal oxide silicon) while most of the signal routing will take place in a nanoscale crossbar switch structure which will be placed on top of the CMOS.